1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device in which a redundancy determining circuit and the like are laid-out efficiently.
2. Description of the Background Art
An example of a conventional semiconductor memory device having redundant memory cells and a redundancy determining circuit will be described.
FIG. 15 is a block diagram representing a configuration of a conventional semiconductor memory device. FIG. 16 shows a specific configuration of a memory block, in which a memory block 113.0 is shown as an example.
Mainly referring to FIG. 15, the conventional semiconductor memory device mainly includes a pair of memory mats MM in the left and right of the figure, a row related circuitry, a row control circuit, a column decoder 115 and a data input/output buffer 116.
Memory mat MM is divided into memory blocks 113.0, 113.1, . . . , 113.m having a plurality of memory cells arranged in a matrix of rows and columns. Memory blocks 113.0, 113.1, . . . , 113.m respectively have normal memory blocks 113.0a, 113.1a, . . . , 113.ma and redundant memory blocks 113.0b, 113.1b, . . . , 113.mb. 
Mainly referring to FIG. 16, normal memory block 113.0a has a plurality of normal memory cells MC arranged in a matrix of rows and columns, and redundant memory block 113.0b has a plurality of redundant memory cells RMC arranged in a matrix of rows and columns. A normal word line WL is connected to gates of normal memory cells MC which are arranged in one same row. The normal word line WL is connected to a normal word driver 112a. A redundant word line RWL is connected to. gates of redundant memory cells RMC arranged in one same row, and the redundant word line RWL is connected to a redundant word driver 112b. The normal memory cells MC and redundant memory cells RMC arranged in the same row are connected to either one of a pair of bit lines BLP, which pair of bit lines BLP are connected to sense amplifier bands 114.0 and 114.1 on the upper and lower portions in the figure.
Mainly referring to FIG. 15, sense amplifier bands 114.0, 114.1, . . . , 114.n are arranged on opposing sides of the plurality of memory blocks 113.0, 113.1, . . . , 113.m, providing a shared sense amplifier scheme. The sense amplifier bands 114.0, 114.1, . . . , 114.n each has a sense amplifier sensing and amplifying data on a column of corresponding memory block when activated.
The row related circuitry is arranged along the longer side of memory mat MM in that area which is between the left and right memory mats MM, and performs operations related to selection of a row of memory cells. The row related circuitry has a row decoder 111 and a word driver 112 provided corresponding to each of memory blocks 113.0, 113.1, . . . , 113.m, and a redundancy determining circuit 101, provided one for each of the pair of left and right memory blocks.
Each row decoder 111 includes a normal row decoder 111a selecting a normal word line WL in the normal memory block, and a redundant row decoder 111b selecting a redundant word line RWL in the redundant memory block. Each word driver 112 has a normal word driver 112a activating a selected normal word line WL, and a redundant word driver 112b activating a selected redundant word line RWL.
Redundancy determining circuit 101 includes, as shown in FIG. 17, a fuse 102a, an NMOS (N channel Metal Oxide Semiconductor) transistor 103, and a redundancy determining signal generating circuit 104. NMOS transistor 103 is connected between a line of ground potential (GND) and redundancy determining signal generating circuit 104, and receives at its gate any of master address signals X4 to X19. Between NMOS transistor 103 and redundancy determining signal generating circuit 104, fuse 102a is connected. The plurality of fuses 102a are arranged in a column, constituting a fuse box 102.
Mainly referring to FIG. 15, the row control circuit has a row predecoder 117 and a row address buffer 118.
Row address buffer 118 outputs a row address signal in response to an external address signal. Row predecoder 117 outputs, based on the output of row address buffer 118, master address signals X4 to X19 which are predecode signals for designating a word line WL.
Data input/output buffer 16 performs signal communication between data I/O pin and each memory block, under the control of column decoder 115.
The master address signals X4 to X19 output from row predecoder 117 are applied to respective redundancy determining circuits 101 over a line extending by the length in the longitudinal direction of the row related circuitry. Further, the master address signals X4 to X19 are passed to a repeater 141 (FIGS. 16, 17) through a line branching from the line extending in the lengthwise direction to be local address signals, which are applied to a normal row decoder 111a. 
The row selecting operation in the conventional semiconductor memory device will be described in the following.
Referring to FIG. 15, row address buffer 118 outputs a row address signal in response to an external address signal.
Row predecoder 117 outputs, based on the output of row address buffer 118, master address signals X4 to X19 for designating a word line WL. The master address signals X4 to X19 are applied to redundancy determining circuit 101, and local address signals from the master address signals X4 to X19 are applied to normal row decoder 111a. 
By the master address signals, a sense amplifier which is in contact with the selected memory block is disconnected from non-selected memory blocks, and an equalizing circuit, which is precharging the potential of the bit lines of the memory block at an intermediate potential VBL, is canceled.
Redundancy determining circuit 101 determines whether redundancy is to be used/not to be used, based on master address signals X4 to X19. When the redundancy is to be used, a normal word line WL including a defective memory cell MC in FIG. 16 is set to a non-selected state, and a redundant word line RWL connected to redundant memory cell RMC to the selected state. The specific operation is as follows.
When there is a defective memory cell MC in the normal memory block, a fuse 102 corresponding to the row address of the defective memory cell MC is blown off (disconnected) by laser trimming (LT) or the like in advance.
Therefore, when the normal word line WL which is activated is not at an address to be replaced by the redundant word line RWL, the fuse 102a corresponding to that address is not blown off. Therefore, when the master address signals X4 to X19 corresponding to the address are input to redundancy determining circuit 101, nodes A and B are short-circuited to GND through NMOS transistor 103, and attain to L level.
When the normal word line WL to be activated is at the address which is to be replaced by the redundant word line RWL, the fuse 102a corresponding to the address has been blown off. Therefore, even when master address signals X4 to X19 corresponding to that address are input to redundancy determining circuit 101, nodes A and B do not attain to the L level but are kept at the H level.
Dependent on the potential levels of nodes A and B, the redundancy determining signal is generated by redundancy determining signal generating circuit 104. Based on the redundancy determining signal and the like, normal row decoder 111a sets the normal word line WL including the defective memory cell MC to non-selected state, and redundancy row decoder 111b selects the redundant word line RWL. Thus the normal word line WL including the defective memory cell MC is replaced by the redundant word line RWL, and the defect is repaired.
In the conventional semiconductor memory device, only one redundancy determining circuit 101 is provided for a pair of memory blocks on the left and right sides of the figure, with row decoder 111 positioned therebetween, as shown in FIGS. 15 to 17. Therefore, when there is a defective memory cell MC in the memory block on the right side of the figure, for example, and the fuse 102a is programmed (blown) to replace the normal word line WL connected to the defective memory cell MC with the redundant word line RWL, the normal word line WL of the same address in the memory block on the left side of the figure has been replaced with redundant word line RWL simultaneously.
In this configuration, however, when there are defective memory cells MC on normal word lines WL of different addresses in the left and right memory blocks, one of the defects cannot be repaired, so that the whole chip must be discarded as defective.
In order to repair larger number of defective memory cells MC within the memory blocks to obtain chips operating normally, it is necessary to prepare larger number of redundant memory cells RMC and to prepare fuses 102a corresponding in number to the redundant memory cells RMC. The fuses 102a, however, are portions which may be blown off by laser trimming, and therefore the fuses 102a cannot be arranged close to each other. Therefore, though the memory cells MC and sense amplifier bands and the like associated therewith can be reduced in size generation by generation along with the progress in microprocessing technique, the fuse box 102 cannot be made smaller.
An object of the present invention is to provide a semiconductor memory device in which fuses are laid-out efficiently, so that circuits are arranged effectively on a chip.
According to an aspect of the present invention, the semiconductor memory device includes a pair of row decoders, a pair of memory blocks and a redundancy determining circuit. The pair of memory blocks are arranged on opposing sides of a pair of row decoders. Each of the pair of memory blocks include a plurality of normal memory cells arranged in a matrix of rows and columns, and a plurality of redundant memory cells arranged at least in one row. The redundancy determining circuit performs replacement of a row of the normal memory cells including a defective memory cell by a row of redundant memory cells, independently in each of the pair of memory blocks.
In the semiconductor memory device, the redundancy determining circuit replaces a defective memory cell independently in each of the pair of memory blocks on opposing sides of the row decoder. Therefore, even when there are defects at rows of different addresses in one and the other of the pair of memory blocks, both defects can be repaired independent from each other, and therefore efficiency of repairment is improved.
Preferably, in the semiconductor memory device in accordance with the above described aspect, the redundancy determining circuit has a plurality of fuse groups, each including a plurality of fuses arranged aligned.
As the fuses are arranged not in one train but in a plurality of trains, the length of the fuse group can be shortened, allowing efficient arrangement of the fuses.
Preferably, in the semiconductor memory device in accordance with the above described aspect, the redundancy determining circuit is arranged in an area between the pair of row decoders. A plurality of lines for applying respective ones of the plurality of master address signals for selecting a row of normal memory cells to the redundancy determining circuit are further provided. The plurality of lines include a first line extending in an area between the redundancy determining circuit and one of the pair of memory blocks and connected to the redundancy determining circuit, and a second line extending in an area between the redundancy determining circuit and the other one of the pair of memory blocks and connected to the redundancy determining circuit.
Therefore, even when the fuses of the redundancy determining circuit are arranged in a plurality of trains, it is possible to apply the master address signals to the fuses in the redundancy determining circuit efficiently.
Preferably, in the semiconductor memory device in accordance with the above described aspect, the redundancy determining circuit has a first redundancy determining circuit unit for replacement in one of the pair of memory block, and a second redundancy determining circuit unit for replacement in the other one of the pair of memory blocks. The plurality of lines for applying respective ones of the plurality of address signals for selecting a row of the normal memory cells to the redundancy determining circuit has a center line extending in an area between the first and second redundancy determining circuit units and connected to the first and second redundancy determining circuit units.
Thus, even when the redundancy determining circuit is divided into first and second redundancy determining circuit units for independently performing replacement of defective memory cells in the pair of memory blocks, it is possible to apply master address signals efficiently to the first and second redundancy determining circuit units.
Preferably, in the semiconductor memory device in accordance with the above described aspect, there are a plurality of blocks in which a pair of memory blocks, a pair of row decoders and a redundancy determining circuit are arranged aligned with each other. The first line is arranged to pass between the redundancy determining circuit and one of the pair of memory blocks in each block. The second line is arranged to pass through the redundancy determining circuit and the other one of the pair of memory blocks in each block. The center line is arranged to pass between the first and second redundancy determining circuit units in each block.
As the first and second lines extend in the area between the memory blocks and the redundancy determining circuit along the lengthwise direction of the redundancy determining circuit, the total length of the first and second lines can be shortened, enabling higher speed of operation.
Preferably, in the semiconductor memory device in accordance with the above described aspect, a repeater is further provided, arranged in an area between adjacent blocks. A branch line branched from the center line is connected through the repeater to row decoders in both of the adjacent one of said blocks.
Thus, it becomes possible to apply the master address signals to the row decoders from the center line extending in an area between the first and second redundancy determining units.
Preferably, in the semiconductor memory device in accordance with the above described aspect, the row decoder in one of the blocks has one side area positioned on the side of the block adjacent to the one of the blocks on one side, and the other area branched from the center line through a repeater located on one side of the one of the blocks. The other side area of the row decoder in one of the blocks is connected to a branch line branched from another center line through a repeater located on the other side of the one of the blocks.
Accordingly, the number of repeaters can be reduced to one half that of the prior art, and therefore gate capacitance of the transistors included in the repeater can be reduced. Further, the total length of the branch lines can be shortened, and hence it becomes possible to reduce the line parasitic capacitance and to suppress line by line variation.
According to another aspect of the present invention, the semiconductor memory device includes a plurality of pads, a circuit for generating a signal having a prescribed characteristic, and a fuse. The fuse is arranged in an area between adjacent ones of the plurality of pads, for tuning characteristic of the signal generated by the circuit.
In the semiconductor memory device, a fuse is arranged between pads where circuits are not much arranged. Therefore, more efficient arrangement of circuits on the chip is possible, as compared when the fuses are arranged in an outer peripheral region of the chip.
Preferably, in the semiconductor memory device in accordance with the above described aspect, the circuit is a reference voltage generating circuit. Thus, efficient arrangement of the circuits is possible when the reference voltage generating circuit is used.
Preferably, in the semiconductor memory device in accordance with the above described aspect, a plurality of blocks each including the pair of memory blocks, the pair of row decoders and the redundancy determining circuit arranged aligned with each other are provided. The semiconductor memory device further includes i) a plurality of lines for transmitting respective the ones of a plurality of address signals for selecting a row of the normal memory cells to the redundancy determining circuit in each of the blocks, ii) a repeater arranged in an area between adjacent ones of the blocks, and iii) a branch line branched from one of the plurality of lines and connected to the row decoders in both of the adjacent ones of the blocks through the repeater.
Preferably, in the semiconductor memory device in accordance with the above described aspect, a plurality of blocks each including the pair of memory blocks, the pair of row decoders and the redundancy determining circuit arranged aligned with each other are provided. The semiconductor memory device further comprises i) a plurality of lines for transmitting respective ones of a plurality of address signals for selecting a row of the normal memory cells to the redundancy determining circuit in each of the blocks, ii) a first repeater located on one side of one of the blocks, and iii) a second repeater located on the other side of the one of the blocks. The row decoder in the one of the blocks includes one side area connected to a branch line branched from one of the plurality of lines through the first repeater and the other side area connected to a branch line branched from the other of the plurality of lines through the second repeater.